1. Field of the Invention
The present invention relates to testing of semiconductor devices, and more particularly to a technique for determining defect density as a function of individual metal layers in a semiconductor process employing multiple metal layers.
2. Description of the Related Art
Integrated circuits have become key components of many consumer and commercial electronic products, often replacing discrete components and enhancing product functionality. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems can now be reduced to a single integrated circuit or application specific integrated circuit (ASIC) device. These integrated circuits (also referred to as "chips") may use many functions that previously could not be implemented together on a single chip, including: microprocessors, digital signal processors, mixed signal and analog functions, large blocks of memory and high speed interfaces. It is a common practice for the manufacturers of such integrated circuits to test device functionality at the manufacturing site. However, the complex nature of today's integrated circuits presents new testing challenges.
Interconnecting the millions of logic gates and megabytes of memory that may be present on a chip also poses difficulties. To aid in this task, new multiple layer metallization schemes have been developed that allow up to five or more distinct "levels" or layers of metal interconnect wires, with pitches of 0.125 .mu.m and tighter on the first few layers. In such multiple layer metallization schemes, the various metal interconnect wires typically have different nominal widths and heights, different distances from transistor gates, and are insulated by oxide layers of varying thickness. The differences in the physical properties of the metal layers cause different metal layers to exhibit somewhat dissimilar electrical characteristics. Further, because each of the metal layers in manufactured in separate process steps involving separate masks, systemic process variations may cause some metal layers to be more susceptible to defects or faults.
Typical metallization faults include undercutting, burnout, open circuits due to electrostatic discharge, and oxide cracks. Additional problems may occur at junction or via structures between metal layers. As known to those skilled in the art, a via is an opening in an insulating layer between metal layers that provides an electrical pathway from one metal layer to the metal layer above or below it. If the etchant used to form an opening in the insulating layer is utilized to excess, a chemical reaction may take place between the underlying metal layer and the etchant. The chemical reaction may result in pin holes in the metal layer, thereby causing a defective via structure. Likewise, if the etchant is under utilized an unwanted layer of insulating material may remain, preventing electrical contact between the metal layers.
When the various metal layers are formed using aluminum-based materials, other problems may exist. Because aluminum is a reactive metal, the use of aluminum can result in the formation of certain undesired compounds such as oxides. Oxides act as an insulator and may prevent the formation of reproducible ohmic contacts between the lower and upper metal layers. Again, since the individual metal layers are formed at different stages of the manufacturing process, process variations at a given step may adversely affect only one or two metal layers or the via structures between them. Isolating such problems can be difficult in multiple layer metallization schemes.
In an to effort avoid interconnect and other problems, an integrated circuit design is typically simulated and verified in a software environment using a variety of CAE and design verification tools, before the integrated circuit is actually fabricated. Such software processes function to reduce costly design iterations because modifications to an integrated circuit design are more readily achieved via software. However, existing software utilizes predetermined manufacturing process information that does not reflect process variations which may give rise to metallization defects or faults.
Once fabricated, integrated circuits or die are typically tested using automated test equipment (ATE). Although device functionality can be verified, production test procedures may not aid a process engineer in determining the precise cause of defects. Integrated circuits having defects entailing vias and metal interconnect wires generally fail functional or parametric testing regardless of the metal layer(s) involved. Therefore, if a process problem develops which causes defects in a given metal layer, production testing may not allow the problem to be accurately pinpointed. If the test strategy employed does not allow the design or process engineers to isolate defects as a function of an individual metal layer, remedial measures are difficult to implement.
One prior method of determining defect density as a function of individual metal layers involves creating separate test die for individual metal layers. The test die are included on production wafers, and predominantly utilize a single metal layer for providing interconnections between test structures. Using such an approach, an integrated circuit using five metal layers requires five separate test die structures. Each of the test die therefore requires a unique mask set. This approach is expensive and necessitates separate production lots using different mask sets in order to correlate faults with specific metal layers. To track process defects, it would be desirable to develop a technique that allows a design or process engineer to determine defect density as a function of an individual metal layer without using a different test die for each metal layer.